This invention relates to a semiconductor device constituting a monolithic semiconductor IC device including a plurality of bipolar transistors formed in a single semiconductor substrate, and a monolithic semiconductor IC device including a bipolar transistor and a MOS transistor in a single semiconductor substrate.
Conventionally, in a Bi-CMOS LSI device (a large scale integrated circuit device including bipolar transistors and complementary metal-oxide-semiconductor field effect transistors), the performance of the constituent bipolar transistors (cutoff frequency f.sub.T and breakdown voltage) is the same throughout the LSI chip. This performance is determined by such a transistor which needs the highest breakdown voltage. The breakdown voltage and the cutoff frequency of a transistor are in the relation of trade-off to each other.
With respect to IC devices which include bipolar transistors other than Bi-CMOS LSI devices, there is a concept, as proposed in JP-A-57-157539, of partially differentiating the thickness of the epitaxial layer to constitute a circuit with bipolar transistors of different operation speed (cutoff frequency) and different breakdown voltage. In this case, the breakdown voltage is made different between bipolar transistors constituting the logic circuit provided with memory portion and bipolar transistors constituting the output linear circuit. In other words, the breakdown voltage is the same for all the bipolar transistors constituting the logic circuit.
The breakdown voltage needed for a bipolar transistor in a monolithic semiconductor IC device differs depending on what part or block of executing various functions the bipolar transistor under interest constitutes.
For example, a monolithic semiconductor IC device constituting a DRAM device may be a Bi-CMOS LSI device including such blocks as disposed as schematically shown in FIG. 1. Namely, the DRAM device includes an input circuit block 15, a decoder block 16, a word line driver block 17, a memory cell block 18, a sense amplifier block 19, and an output circuit block 20.
In the DRAM device constructed as above, the input circuit block 15 and the output circuit block 20 are formed only of those bipolar transistors which operate in the small signal region (the small signal being, for example, a voltage signal having an amplitude of about 1 V or lower) in order to improve the operation speed. The decoder block 16, the word line driver block 17 and the memory cell block 18 have circuit structures including CMOS transistors in order to reduce the power consumption and to increase the degree of integration. Here, however, the decoder block 16 and the word line driver block 17 also include bipolar transistors operating in the large signal region (the large signal being, for example, a voltage signal having an amplitude corresponding to about 0.8 to 1.2 times the supply voltage to the device) because there is a necessity to drive a multiplicity of memory cells at a high speed. The sense amplifier block 19 may also include bipolar transistors operating in the large signal region.
Now, a specific structure of the DRAM device having the structure as described above will be described referring to FIG. 2.
In the figure, numeral 11 denotes a bipolar transistor, 12 a p type MOSFET (hereinafter, referred to as PMOS), 13 an n type MOSFET (hereinafter, referred to as NMOS), and 14 a memory cell.
The bipolar transistor 11 is particularly that transistor which constitutes an input/output circuit for the memory cell, and operates in the small signal region (i.e. handles small amplitude signals). The PMOS 12 and the NMOS 13 constitute a CMOS by connecting one of their drain terminals with one of their source terminals.
Numeral 6 denotes a p type semiconductor substrate in the surface of which an n.sup.+ type embedded layer 7 and a p.sup.+ type embedded layer 9 are formed by the conventional technique such as ion implantation or diffusion.
On the embedded layers, an n type well region 8-1 (n type epitaxial layer) which constitutes a collector region of a bipolar transistor, an n type well region 8-2 (n type epitaxial layer) which constitutes a channel layer of the PMOS, and a p type well 10 (p type epitaxial layer) are formed by the technology of the epitaxial growth.
On the n type wells 8-1, 8-2 and the p type well 10, semiconductor regions 71, 72, 73, 74, 75, 76 and 77 are formed through ion implantation or diffusion.
A field insulating film 31 for isolating the elements from one another is formed for example of SiO.sub.2 by selective thermal oxidation.
Numeral 33 denotes electrodes for the respective elements, which electrodes are formed by applying an inter-layer insulator film 32 on the whole surface, then opening windows for contacting electrodes by dry etching, vacuum-depositing a thin film of metal such as aluminum (Al), and removing those portions of the aluminum thin film by etching which are between the elements.
Here, in the conventional Bi-CMOS LSI device as described above, the n type well regions 8-1 which constitute the collector regions of the bipolar transistors 11, are formed under the same conditions and have the same thickness and the impurity concentration, regardless of whether the transistor should operate in the small signal region or in the large signal region. Further, the conditions for forming the n type well region 8-1 are also the same as those for forming the n type well region 8-2 which constitutes the channel layer of the PMOS 12. Thus in the LSI, the impurity concentration in the n type well region 8-1 is the same as that in the n type well region 8-2.
Now, referring back to FIG. 1 again, the breakdown voltage required for the respective blocks will be described. For example, the bipolar transistors in the circuit blocks 17 and 19 directly connected to the memory cell block 18 should have a breakdown voltage of 8 volts or more. The bipolar transistors in the indirect peripheral circuit block 16 need a breakdown voltage of 5 volts or more. The bipolar transistors in the ECL (emitter coupled logic) circuit block included in the IC device should have a breakdown voltage of around 3-4 volts. As stated above, the cutoff frequency f.sub.T which is a measure of the high speed operation and the breakdown voltage in a bipolar transistor are in the mutual relation of trade-off. To make the breakdown voltage of a bipolar transistor high is to put a disturbance for making the operation speed of the bipolar transistor high (i.e. the cutoff frequency cannot be made high). Therefore, to make the breakdown voltages of all the bipolar transistors in a single LSI chip uniform constitutes a burden for increasing the operation speed of the monolithic IC device.
Also, as the impurity concentration of the collector region of a bipolar transistor is made higher, the larger becomes the possibility of increasing the operation speed thereof. As will be stated later, however, the operation speed of the monolithic IC device including the bipolar transistor is not necessarily improved.